PMOD from PL instead of PS

Questions and discussions about Xillinux

PMOD from PL instead of PS

Postby Guest » Thu Dec 05, 2019 8:50 pm

Hi,
I'm new to this whole system (Zynq, Xillinux, HLS), but have done some HDL stuff before.

I've gone through the following:
http://xillybus.com/downloads/doc/xillybus_block_design_flow.pdf
and am trying now to do something (slightly) similar with some external hardware connected to a PMOD on my zedboard.

I get how to talk to the GPIO through Linux, but would need to have this take place on the PL side instead of the PS. The flow would be as follows:
External hardware generating some data -> PMOD GPIO -> PL doing some math on the inputs -> signal to PS when calculation is done.

From everything I have read in the tutorials, documents, and forums, I still do not know how to go about this....
1. How do I modify the design so that a PMOD (ex. JA) is routed to the PL and not the PS?
2. How would I then route the "freed up" PMOD into the Xillybus block as an input? It would be an input to a block like the tutorial in the link, which would then send its data out to "to_host_read_32".
Guest
 

Re: PMOD from PL instead of PS

Postby support » Fri Dec 06, 2019 4:46 am

Hello,

Please refer to section 5.4 ("Taking over GPIO I/O pins for PL logic") in Getting started with Xillinux for Zynq-7000 EPP:

http://xillybus.com/downloads/doc/xilly ... d_zynq.pdf

I should mention that if you have some experience with HDL design, the Block Design flow is less recommended.

Regards,
Eli
support
 
Posts: 733
Joined: Tue Apr 24, 2012 3:46 pm

Re: PMOD from PL instead of PS

Postby Guest » Fri Dec 06, 2019 6:53 pm

Hi Eli,

Thanks for the response.
I've already gone through that document, but some things are still unclear to me:

I have created a module (test.v) with bus signals test_io_out (4 bits), test_io_in (4 bits), and return_to_PS (32 bits) . I have modified the .xdc file to have the last 8 PS_GPIO assignments to be replaced with these. Where in the design do I connect this module? (return_to_PS would be feeding data to /dev/xillybus_read_32)
Guest
 

Re: PMOD from PL instead of PS

Postby support » Sat Dec 07, 2019 12:54 am

Hello,

I take it that you've created a Verilog file with the functionality you want, and now you want to connect it to the Xillybus block. For that, you need to create an AXI Streaming interface in the Verilog module for the data flow, and then generate a Vivado block for that piece of logic. Please consult with Xilinx' documentation and possibly their forums on this matter.

Alternatively, give the block design flow a royal kick in the bottom, and go for the mainstream FIFO interface instead. Recommended.

Regards,
Eli
support
 
Posts: 733
Joined: Tue Apr 24, 2012 3:46 pm


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