Changing HLS expample.
Posted:
Hello,
I succesfully executed the given HLS example for the
Of course I wanted to make some changes and the first obvious and easiest change is to change sine function for cosine. I just changed next lines:
Then I made the same procedure to synthetize and to generate the bitstream on ISE as the given example.
The problem arrives when I test it on the Zedboard. It seems that this time the generated custom IP cores "does'nt do anything", because I get back something like this:
Instead of 124 and 0.707... as before.
Obviously I am missing something, but I do not really know, the mycalc function is simple as the whole code, so I guess it is a detail I am ignoring.
Thanks in advance for your help.
I succesfully executed the given HLS example for the
- Code: Select all
int mycalc(int a, float *x2)
Of course I wanted to make some changes and the first obvious and easiest change is to change sine function for cosine. I just changed next lines:
- Code: Select all
extern float cosf(float); //instead of sinf(float)
int mycalc(int a, float *x2) {
*x2 = cosf(*x2); //instead of sinf(*x2)
return a + 1;
}
Then I made the same procedure to synthetize and to generate the bitstream on ISE as the given example.
The problem arrives when I test it on the Zedboard. It seems that this time the generated custom IP cores "does'nt do anything", because I get back something like this:
- Code: Select all
FPGA said:123 + 1 = 123 and also sin(0.78539816) =0.78539816
Instead of 124 and 0.707... as before.
Obviously I am missing something, but I do not really know, the mycalc function is simple as the whole code, so I guess it is a detail I am ignoring.
Thanks in advance for your help.