Changing HLS expample.

[AtheneNoctua]

Hello,

I succesfully executed the given HLS example for the

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int mycalc(int a, float *x2)

function and tested it on my Zedboard. Everything works as expected.

Of course I wanted to make some changes and the first obvious and easiest change is to change sine function for cosine. I just changed next lines:

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extern float cosf(float); //instead of sinf(float)

int mycalc(int a, float *x2) {
  *x2 = cosf(*x2); //instead of sinf(*x2)
  return a + 1;
}

Then I made the same procedure to synthetize and to generate the bitstream on ISE as the given example.

The problem arrives when I test it on the Zedboard. It seems that this time the generated custom IP cores "does'nt do anything", because I get back something like this:

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FPGA said:123 + 1 = 123 and also sin(0.78539816) =0.78539816

Instead of 124 and 0.707... as before.

Obviously I am missing something, but I do not really know, the mycalc function is simple as the whole code, so I guess it is a detail I am ignoring.

Thanks in advance for your help.

[support]

Hello,

You didn't mention which tool you used to build the logic. If it was ISE -- make sure that you've replaced the files and cleaned the project before re-implementing.

In Vivado, it's indeed a bit more trickier to track down where the actually used sources are located, since Vivado sometimes makes copies of the sources. The easiest way to tell is to open a source file in the GUI and look at the file name that shows on the screen.

Generally speaking, it's always best to clean the project before re-attempting, or you may find yourself with old leftovers.

Regards,
Eli

[AtheneNoctua]

Hello Eli,

Actually I use ISE to build the logic. Quickly I realized that re-building projects in ISE is a mess for all the old and new files generated, so I am using a clean project of Xillybus and just copy it everytime I intend to make a new HLS project.

Just realized that I get the very same problem without even changing the sinf function, so I guess the problems comes from ISE and not from HLS. I will make a few test and will post the results.

[AtheneNoctua]

Hello,

I finally realized my mistake. The problema was that I was using the project built before the changes on the verilog code as stated in http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-4 in section "Modify the Xillydemo file". Not doing that was resulting in not having the HLS Wrapper, FIFOS and Xillybus wrapper in the final logic.

For reference, I am posting below the code for calculating sin and cosin in the same logic, I just changed a few lines in the main.c code of HLS example. I just made a few simple test on the Zedboar and it is workin fine so far.

My next goal is to syntethize a 32-point FFT, advices?.

Thanks.

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#include <math.h>
#include <stdint.h>
#include "xilly_debug.h"

extern float sinf(float);
extern float cosf(float);

void mycalc(float *x1, float *x2) {
  *x1 = sinf(*x1);
  *x2 = cosf(*x2);
}

void xillybus_wrapper(int *in, int *out) {
#pragma AP interface ap_fifo port=in
#pragma AP interface ap_fifo port=out
#pragma AP interface ap_ctrl_none port=return

  uint32_t tmp1, tmp2;
  float x1, x2, y1, y2;

  xilly_puts("Hello, world\n");

  // Handle input data
  tmp1 = *in++;
  tmp2 = *in++;
  x1 = *((float *) &tmp1); // Convert uint32_t to float
  x2 = *((float *) &tmp2); // Convert uint32_t to float

  // Debug output
  xilly_puts("x1=");
  xilly_decprint(x1, 1);
  xilly_puts("\n");

  // Run the calculations
  mycalc(&x1, &x2);
  y1 = x1; // This helps HLS in the conversion below
  y2 = x2; // This helps HLS in the conversion below

  // Handle output data
  tmp1 = *((uint32_t *) &y1); // Convert float to uint32_t
  tmp2 = *((uint32_t *) &y2); // Convert float to uint32_t
  *out++ = tmp1;
  *out++ = tmp2;
}


[support]

Hi,

Good to know it sorted itself out.

As for going further, my only advice is to read through the coding style guidelines in Xilinx' documentation, before attempting to write code. Really, do. Many trivial features of C and C++ are simply not allowed in synthesizable C/C++.

Regards,
Eli

[AtheneNoctua]

Hello,

Thanks for the advice. I found this guide: http://www.xilinx.com/support/documenta ... thesis.pdf

As I told before, I made a little change in the hlsdemo code, I am able to run correctly a sin and cosin function in the Zedboard, I provided the code above.

Now I am trying to test little pieces of a bigger code I am trying to implement. In this case I am trying to give the FPGA 2 floats and retrieve the square root of those floats. I just made a little change in the later code, just changing these lines

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//extern float sinf(float);
//extern float cosf(float);
extern float sqrtf(float);

void mycalc(float *x1, float *x2) {
  *x1 = sqrtf(*x1);
  *x2 = sqrtf(*x2);
}


I write the entire code at the end of this entry.

"sqrtf" is supported for synthesis while originally "sqrt" not.

When I activate solutions it seems that it works correctly, but then I get errors when using the ISE to generate the bitstream.

ERROR:HDLCompiler:1654 - "C:\...\hls-starter-1.0\coprocess\example\syn\verilog\xillybus_wrapper_fsqrt_32ns_32ns_32_12.v" Line 35: Instantiating <xillybus_wrapper_ap_fsqrt_10_no_dsp_32_u> from unknown module <xillybus_wrapper_ap_fsqrt_10_no_dsp_32>

I checked that with sqrtf I get 8 .v files, while in the sin and cosin I got 13 .v files.

I would really appreciate some help to address this problem with the "missing" (I guess) .v files.

Thanks in advance.

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#include <math.h>
#include <stdint.h>
#include "xilly_debug.h"

//extern float cosf(float);
extern float sqrtf(float);

void mycalc(float *x1, float *x2) {
  *x1 = sqrtf(*x1);
  *x2 = sqrtf(*x2);
}

void xillybus_wrapper(int *in, int *out) {
#pragma AP interface ap_fifo port=in
#pragma AP interface ap_fifo port=out
#pragma AP interface ap_ctrl_none port=return


  uint32_t tmp1, tmp2;
  float x1, x2, y1, y2;

  xilly_puts("Hello, world\n");

  // Handle input data
  tmp1 = *in++;
  tmp2 = *in++;
  x1 = *((float *) &tmp1);
  x2 = *((float *) &tmp2); // Convert uint32_t to float

  // Debug output
  xilly_puts("x1=");
  xilly_decprint(x1, 1);
  xilly_puts("\n");

  // Run the calculations
  mycalc(&x1, &x2);
  y1 = x1;
  y2 = x2; // This helps HLS in the conversion below

  // Handle output data
  tmp1 = *((uint32_t *) &y1);
  tmp2 = *((uint32_t *) &y2); // Convert float to uint32_t
  *out++ = tmp1;
  *out++ = tmp2;
}

[support]

Hi,

I really suggest asking HLS related questions on Xilinx' forum -- this forum is intended for purely Xillybus issues.

Anyhow, HLS generates a different number of Verilog files, depending on the content of the C program. I don't think there are "missing" files. The question is if you properly updated the ISE project with the files that were generated.

Regards,
Eli

[AtheneNoctua]

Hello Eli,

I was hesitant between asking here or in Xilinx forums. I thought it could be something with "xilly_debug.h" so I asked here.

I think I am loading all the files correctly on ISE. Looking at the error

ERROR:HDLCompiler:1654 - "C:\...\hls-starter-1.0\coprocess\example\syn\verilog\xillybus_wrapper_fsqrt_32ns_32ns_32_12.v" Line 35: Instantiating <xillybus_wrapper_ap_fsqrt_10_no_dsp_32_u> from unknown module <xillybus_wrapper_ap_fsqrt_10_no_dsp_32>

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xillybus_wrapper_ap_fsqrt_10_no_dsp_32 xillybus_wrapper_ap_fsqrt_10_no_dsp_32_u (
    .aclk                 ( aclk ),
    .aclken               ( aclken ),
    .s_axis_a_tvalid      ( a_tvalid ),
    .s_axis_a_tdata       ( a_tdata ),
    .m_axis_result_tvalid ( r_tvalid ),
    .m_axis_result_tdata  ( r_tdata )
);

I can see that actually the "xillybus_wrapper_ap_fsqrt_10_no_dsp_32" was not generated by HLS, and the desing view show it with a question mark:



Indeed there is no "xillybus_wrapper_ap_fsqrt_10_no_dsp_32_u.v" in the directory of generated files, but there is a "xillybus_wrapper_ap_fsqrt_10_no_dsp_32_ip.tcl" file.

I will keep trying to figure it out.

Thanks for you help.

[Guest]

Hello,

It seems that indeed those tcl files are the ones generated by HLS to use the DSP slices of the Zynq.

The problem here is that, it seems, that only in Vivado is possible to synthetize those designs, but Vivado will not generate the bistream for the Xillybus. The custom Xillybus project bistream is only possible to generate with ISE, right?

I would like to make a direct question, it is possible to generate a custom project in Xillybus with HLS that is able to operate over floats (add, substract, multiply and sqrt)?

Thanks.

[support]

Hi,

From a Xillybus point of view, anything that can be built with ISE goes with Vivado as well. The HLS tutorial was written when Vivado was really new, and before Xillybus' bundles supported it (and it's inclined towards older device, which are pretty outdated these years).

So maybe give Vivado a go. Look at the "Getting Started" guides on the documentation section. The flow is pretty similar.

Regards,
Eli