by Guest »
Respected sir,
The existing 32x504 fifo changed to 32x504 and 8x2048 fifo.
made following changes
original in xillidemo.v
// 32-bit loopback
/*
fifo_32x512 fifo_32 //write 32 bit read 32 bit
(
.clk(bus_clk),
.srst(!user_w_write_32_open && !user_r_read_32_open),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(user_w_write_32_full),
.empty(user_r_read_32_empty)
);
assign user_r_read_32_eof = 0;
*/
changed to
fifo_32x512 fifo_32 //write 32bit read 8 bit
(
.rst(!user_w_write_32_open && !user_r_read_8_open), // input rst
.wr_clk(bus_clk), // input wr_clk
.rd_clk(bus_clk), // input rd_clk
.din(user_w_write_32_data), // input [31 : 0] din
.wr_en(user_w_write_32_wren), // input wr_en
.rd_en(user_r_read_8_rden), // input rd_en
.dout(user_r_read_8_data), // output [7 : 0] dout
.full(user_w_write_32_full), // output full
.empty(user_r_read_8_empty)); // output empty
assign user_r_read_8_eof = 0;
/**********************************************************************/
FIRST dos prompt
> writestream \\.\xillybus_write_32
ABCDEFGHIJKLMNOPQRSTUVWXYZ
SECOND dospromt
> readstream \\.xillybus_read_08
DCBAHGFELKJIPONMTSRQXWUV
/**********************************************************************************/
The read out is not in order
ABCD is read as DCBA
EFGH is read as HGFE and so on
FIFO write width = 32
FIFO read width = 8
kindly guide
regards
mks