Vivado 2016.2
Ubuntu 16.04.1
AC701
Custom IP core utilizing 2 separate dual access memory.
1) bulk data
2) control data
Basically, I am trying to make a low latency sound card using xillybus. Total data rate of data written to the FPGA is 0.7056 MB/s, but I am trying to write 8192 Byes at 86 Hz intervals. In terms of audio programming this chuck of data (8192 Bytes) is considered a "period". On the FPGA, I store 2 periods worth of data. The C-program sits in a loop reading control_data until it signals more data is needed (4 Bytes at a time, basically just increments this 32 bit number when done with a period (half of the 2 periods of storage)). The problem is that sometimes it isn't fast enough and completely misses a few periods before more data is written. The FPGA continuously loops through the 2 periods, so if data isn't written in time it will re-read over old data. Completely unacceptable for my application. At worst a missed period per hour would be ok.
Any help or suggestions would be greatly appreciated. Also, I am not necessarily sure if the problem is xillybus per se, but I need help determining the root of the problem.
Thank you,
Richard