first of all, you have done a very good job with xillybus and there is a lot of documentation to read from.
I'm using Zedboard and Xillinux/Xillybus to accelerate an operation. I've modified xillydemo.vhd to integrate my HW accelerator. I've broken the loopback of the demo, create another 32x512 FIFO using the same component in xillydemo.vhd and put my accelerator in between the two FIFOs. The host write on one FIFO and read from the other one. The accelerator read from the first and write the result to the second FIFO. I think this is the normal way of using Xillybus for coprocessing.
Vivado generates correctly the bitstream but the problem is on the execution of my system. When I try to read from the respective read file on the host, I have no result. I don't know how to fix this. I've read the documentation on Xillybus website and simulated my accelerator separately and it works. So, for sure, the problem is in my comprehension on how to integrate custom vhdl with xillybus.
I have another question : why vivado complains if I use as clock for my accelerator bus_clk?
I put here the xillydemo.vhd portmap of my setting :
- Code: Select all
-- 32-bit FIFO (host to fpga)
fifo_32_hf : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => rd_en,
dout => din_std,
full => user_w_write_32_full,
empty => empty_read
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
din <= unsigned(din_std);
-- ACCELERATOR
acc0 : ACCELERATOR
port map(
clk => clk,
srst => reset_32,
empty_read => empty_read,
full_write => full_write,
din => din,
dout => dout,
rd_en => rd_en,
wr_en => wr_en
);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
-- 32-bit FIFO (fpga to host)
fifo_32_fh : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => dout_std,
wr_en => wr_en,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => full_write,
empty => user_r_read_32_empty
);
dout_std <= std_logic_vector(dout);
user_r_read_32_eof <= '0';
Thanks for your help!