Several questions came to my mind, which is as follows.
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Backgrounds for my circumstances
: I use,
- Xilinx KC705 FPGA dev. kit,
which has 2ch 14-bit 250 MHz ADC,
- Upstream(FPGA->Host PC)
- Intel i7-4790K
- DDR3 RAM 32 GB (Dual Channel)
- Samsung 960 pro SSD (Expected)
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1. Currently, my data rate is 2*14(bit)*250(MHz)=7 Gbps=834 MB/s.
I think ADC should be 10 or 12-bit accuracy since Xillybus Rev.A maximum rate is upto 800 MB/s.
Although, it would be nearly 600 MB/s, which is too fast to save onto storage.
The thing more worse than that is even non-binary choice(10,12-bit) is not fit into
xillybus input data bus width, so I could only make it 8 or 16-bit to fit in.
(8-bit is too low accurate, 16-bit case has too much data)
So now I fill extra 2 bits with 0's making it 16-bit(14bit data+00).
Is there any solution to load 14-bit on 16-bit bus without bandwidth loss like serial-communication packet?
2. If the answer is "No" to Q#1, I would like to use 16-bit bus.
My data is continuous stream and I don't have real-time processing program yet and don't know how to.
Hence, I need to store raw data essentially 1 minute and upto 10 min. if possible.
But I read the opinions on documentations that it must be tough due to limitations on Host PC.
I searched some storage devices and I found recent PCIe NVMe 3.0 SSD has writing speed about 2100 MB/s.
Do you think it could cover 1 GB/s (16-bit 2ch 250 MHz stream) continuous stream for few minutes?
How about your opinion?
3. I read a tutorial about speed test, it said "Don't load the storage."
Currently, I test normal SSD with 450 MB/s writing speed,
It seems like around 200 MB/s with dd command.
(dd if=\\.\xillbyus_read_32 of=ssd storage\first bs=1M count=1000)
Here, Does buffer size mean user-application memory(buffer) size in the host application manual?
Does it affect a lot on speed? I don't understand why it is so slow considering few counts.
(Should Windows be installed on primary SSD? CPU Usage is not much and it is i7 octa core)
4. For Windows user, where can I find the device file (ex:\\.\xillybus_read_32).
I couldn't find such file on any drives..
5. I read few papers on FPGA-PCIe-GPU processing, which is extremely fast since it is not via Host CPU cache.
I doubt if you knew any of this kind of processing or xillybus could approach this manner.
Thank you for reading such a long stories.