[Demo bundle] Find a spare output pin to connect to external

Questions and discussions about the Xillybus IP core and drivers

[Demo bundle] Find a spare output pin to connect to external

Postby Guest »

Hi, dear support,

I'm user of Xilinux demo bundle. However, now we need to connect the Xilinux over ZYBO to external LED panel which is driven by a customized led controller RTL design. Thus, it requires to have ONE output pin for the external connection. Thus, I opened the xillydemo.sdc but it seems all are occupied by the ARM PS_GPIO* in PMODx. I don't know what PINs I can use under Xilinux is working.

So, would you please guide me how to sort out available PIN for output pad driving by internal LED controller for Xilinux over ZYBO if we use the Xilinux demo bundle ?

Thanks
Guest
 

Re: [Demo bundle] Find a spare output pin to connect to exte

Postby support »

Hello,

Please refer to section 5.4, "Taking over GPIO I/O pins for PL logic" in the Getting Started Guide:

http://xillybus.com/downloads/doc/xilly ... d_zynq.pdf

Regards,
Eli
support
 
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Re: [Demo bundle] Find a spare output pin to connect to exte

Postby Guest »

Hi,

I have run into a similar problem and followed the guide to replace a range of PS_GPIO[55:48] pins.
The problem though is that it now reports "5 pins" not meeting the time constraints - and I have no idea why.
I have replaced every reference to PS_GPIO with the with [47:0] or 48, and there are no other warnings or errors about that.

For reference, I am trying to free 8 pins on a single row, from JC and JD for a Digilent Pmod SSD display for debugging.
Guest
 

Re: [Demo bundle] Find a spare output pin to connect to exte

Postby support »

Huh? Timing constraints on the PS_GPIO pins? Where did they come from? Definitely not from the Xillinux bundle.

So the first thing to look at is exactly which constraint failed, and trace its origin. Have a look on the timing report.

Regards,
Eli
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