First, I'm having trouble finding your example fifo.c that I read about here and there. Where do I find it? It wasn't in http://xillybus.com/downloads/appcompiler.tar.gz or at http://xillybus.com/doc/microblaze-xillybus-trivial . Thanks.
Second, I'm concerned about the following. If I have a 32-bit wide FIFO in my FPGA, that connects to Xillybus at 32-bits wide, it will eventually come out a named pipe that reads 8-bit characters. If the FPGA pushes in a single 32-bit word, then the linux application will read 4 bytes. But a billion access later, with interruptions and this and that... My 40yr experience gut tells me to worry about keeping that in sync. I'm concerned I may get to the point where the application is 2 bytes off and reading the last 2 bytes of a previous 32-bit word, along with the first 2 bytes of a subsequent 32-bit word.
Do you have a built-in or preferred method for ensuring such sync?
Third, I might want to use a synchronous stream for a low-bandwidth GPIO interface of my FPGA. I imagine that making the stream synchronous should substantially or eliminate any concerns over 8-bit position synchrony within 32-bit words. I want to be sure I get "live" GPIO from FPGA to host, anyway. I don't easily find doc just yet on exactly HOW the interface between Xillybus and my FPGA fabric works for a synchronous stream. I imagine you may have an extra side signal to request that my FPGA fabric push a value onto the fifo to Xillybus. But I don't want to make an assume/out/of/and. I can't find doc on how my FPGA fabric must act differently for a synchronous stream, or how my FPGA fabric doesn't act differently and therefore what must I do to make sure that "live" GPIO data is received by the linux application when it does a read.
Thanks,
Helmut
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