Eli,
I have a specific question after a bunch of setup.
We have two custom boards. One board works pretty good, except that it generally takes two cold starts to get our board to show up on linux lspci. That is, after the first cold start, the board doesn't show on lspci, then after a second cold start, it does. After a third cold start, it often doesn't show up again; then after a fourth cold start, it does show up on lspci. Note this is a PCIe/104 stack and "cold start" means we power cycle the host computer and FPGA at the same time. Note that we're pretty sure we've eliminated FPGA config speed vs SBC (BIOS) power up.
The second custom board, presumably identical to the first, won't get recognized by lspci no matter what we do.
Either way, we've tested numerous things. We did find something concerning in the xillybus_fpga_api.pdf on page 16, section 4.4 Capture control. It says "The capture_en signal works as a write enable signal for the captured data. There are two situations in which capturing should not take place".
Well, we are putting data into a fifo going to the xillybus_ins, and we're doing that right away.
QUESTION: I don't believe this should be the case, but is it possible that there's ANYTHING we might be doing on our end of the fifos that go into xillybus_ins, that could possibly cause the x4 link to not come up and therefore the board to not show up on lspci. I don't think there should be, but because of the sentence quoted above, I'm a little concerned.
Thanks very much,
Helmut
P.S. We meet timing but have been working on confirming and even adding constraints. Improvements but no 100% success yet. We're not sure what other avenues to test...