Hi, dear support,
I encountered a problem while porting Xillinux over ZYBO FPGA. The customized IP we developed has integrated into the Xilinux over ZYBO and works fine. Also, the IP utilizes some BRAMs in FPGA which the ARM9 can read or write the BRAM before enabling the IP. However, there is a spec run change of the IP which means to increase the size of the BRAM used by the IP. After the run change, the BRAMs are not enough and therefore we come up with to place the data in DRAM first by CPU and then use DMA to move the data into the local buffer inside the IP to resolve the issue. It turns out to need to change the design against the previous way. What I planned to modify is as follows :
1.Change to add the interface of the IP with one extra DMA interface
2.The DMA interface can access DRAM and write to internal SRAM of the IP
My question is : for such kind of spec over Xilinux (We'd like to leverage Xilinux again), I need your guidance to provide me some references on this which I can refer to change the RTL design accordingly. Thanks