Critical warning with block design

Questions and discussions about the Xillybus IP core and drivers

Critical warning with block design

Postby Guest » Fri Dec 14, 2018 9:47 am

Hey there,

I run Xillybus for Ultrascale+ with block design and get this critical warning:

[filemgmt 20-1440] File 'blockdesign/blockdesign/ip/core/xillybus_core.edf' already exists in the project as a part of sub-design file 'blockdesign/blockdesign/ip/blockdesign_xillybus_bundled_0_0/blockdesign_xillybus_bundled_0_0.xci'. Explicitly adding the file outside the scope of the sub-design can lead to unintended behaviors and is not recommended.

What to do?
Guest
 

Re: Critical warning with block design

Postby support » Fri Dec 14, 2018 10:02 am

Hello,

This warning can be ignored safely. The issue is with the EDIF file which is included in the Xillybus block design component, however this doesn't cause any confusions if the replacement of the block design with a custom one (from the IP Core Factory) is done according to the instructions.

Regards,
Eli
support
 
Posts: 653
Joined: Tue Apr 24, 2012 3:46 pm

Re: Critical warning with block design

Postby Litchford » Tue Dec 18, 2018 1:30 pm

Hi Eli, is there a fix for this warning so that it stops showing up? I'd like to get rid of it even if it's safe to ignore.
Litchford
 
Posts: 1
Joined: Mon Dec 17, 2018 10:18 am

Re: Critical warning with block design

Postby support » Tue Dec 18, 2018 3:24 pm

Hello,

Vivado allows demoting critical warnings into messages with lower level. This can be done with GUI, or with set_msg_config -new_severity Tcl commands.

This issue will be fixed on the next update of bundles. The said critical warning appeared on relatively recent versions of Vivado.

Regards,
Eli
support
 
Posts: 653
Joined: Tue Apr 24, 2012 3:46 pm


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