by support »
Hello,
The problem you describe is related to Xilinx' PCIe block. I would suggest trying Gen1, Gen2 and Gen3, possibly change the lane count as well as the device's identification info, in particular the Class. Creating an example design from the existing PCIe block in Xillybus' design can be a good start. See if the device enumerates.
Once you've figured out what the problem is and found a solution, you may migrate it into Xillybus' design. There is a section in the Getting Started guide for Xilinx on making changes to the physical parameters, if necessary.
What you definitely can't change, is the width of the data signals between the PCIe block and Xillybus' IP core. Actually, you can, but that requires another Xillybus IP core revision.
Xillybus' IP core doesn't care about the parameters of the PCIe block. However changes in the PCIe block's parameter might require changes in the design's timing constraints, which is the delicate part in this whole manner.
And another thing to be aware of: There is an annoying bug (or is it a feature?) that Vivado's GUI resets the device's Vendor / Product IDs to default every time some change is made to the parameters. That too can lead to some confusion.
Regards,
Eli