Changing PCIe link speed and

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Changing PCIe link speed and

Postby mwayne »

Hello,

I have a working XL core, Gen2 and x8 lanes. It currently runs on a XC7K160T-3 speed grade FPGA.

I need to adapt to a XC7K160T-1 speed grade FPGA. I have two options, keep x8 lanes and move to Gen1, or keep Gen2 and go to x4 lanes. (pg054, table 2-4).

Two questions.

1. First, is the XL core compatible with these changes? Or should I be sticking with the initial Rev A core?

2. I'm having a bit of trouble doing this when attempting to stay at x8 lane and move to Gen2. I'm following the steps outlined in Section 4.5 of the Getting Started with the FPGA demo bundle for Xilinx, but so far I'm not meeting timing. Is it easier to change the link speed, or to change the lane numbers?

Thank you
mwayne
 
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Re: Changing PCIe link speed and

Postby support »

Hello,

Given that Kintex 7 devices with -1 speed grade have no problem with Gen2, I take it that the purpose of this change is to reduce the bus_clk frequency from 250 MHz to 125 MHz, and by doing so, solve a timing constraint issue.

So to answer your question, none of the IP cores care about what happen with the PCIe block (as long as it works), so reducing the lane count and/or speed will work fine. The reduction of the frequency is fine as well.

I should mention however that if there's a chance that a license will be purchased for this core in the future, you should consider a rev. B core, as the price for XL is generally higher (even though not dramatically).

Another thing is that reverting to rev. B might by itself solve the timing problem, because the XL core is heavier and consumes more routing resources. But I can't tell if that will help.

As for your second question, I suppose you meant staying at x8 and move to Gen1. If you don't meet timing, where are the failing paths? If they are outside the PCIe block, then you probably haven't done the transition correctly, because the whole point is to reduce bus_clk. However if they are inside the PCIe block, I would suggest trying to set up Xilinx' demo design for PCIe with these parameters, and see if that passes timing. If not, there's probably not much to do.

Regards,
Eli
support
 
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Re: Changing PCIe link speed and

Postby mwayne »

'Given that Kintex 7 devices with -1 speed grade have no problem with Gen2 ... '

Well the purpose is just to translate a very simple design that works on a -3 Kintex 7 over to the -1 Kintex 7, which are easier to find these days with the chip shortage going on.

According to to pg054 Table 2-4, they 'don't' in fact handle x8 lane Gen 2 designs unless you have a -3. Image attached below.

http://imgur.com/a/Q3jcNT4

This may be a stupid question, but 5.0 GT/s is Gen 2 and 2.5 GT/s is Gen 1, correct?

At any rate, thank you for the information. I will try to reduce the number of lanes first, and avoid changing timing information unless I have to.
mwayne
 
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Re: Changing PCIe link speed and

Postby support »

Hello,

As I said, there's no problem with Gen2 (which is indeed 5 GT/s and Gen1 is 2.5 GT/s). But I didn't notice that Gen2 x8 is indeed limited to higher speed grades... ;)

Thanks for clarifying.

Regards,
Eli
support
 
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