Hi Eli,
I am using a vc707 board and trying to replace inferred RAM in the reference design (32 bit) with a Dual Port Ram.
I have used the following code:
-------------------------------------------
my_dpram : dpr_32bx16a
PORT MAP (
clka => bus_clk,
ena => '1',
wea => wea,
addra => user_mem_32_addr,
dina => user_w_mem_32_data,
douta => user_r_mem_32_data,
clkb => dpram_clk,
enb => dpram_en,
web => dpram_we,
addrb => dpram_addr,
dinb => dpram_data_in,
doutb => dpram_data_out
);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_32_wren = '1') then
wea(0) <= '1';
end if;
if (user_r_mem_32_rden = '1') then
wea(0) <= '0';
end if;
end if;
end process;
user_r_mem_32_empty <= '0';
user_r_mem_32_eof <= '0';
user_w_mem_32_full <= '0';
----------------------------------------------
My problems are:
-I can read and write from side b which is my own design, but when I write from Xillybus side(side a) using >memwrite \\.\xillybus_mem_32 0 ,it doesn't write.
-When I write ,for example "deadbeef" ,from side b and read it from side a using >memread \\.\xillybus_mem_32 0, the result value is "ef" . When I read the memory values from address 1,2 and 3; all of them are the same value as the address 0 which is "ef" which should be "be","ad" and "de" respectively.
- I used hexdump and I saw it reads memory values correctly.
How can I solve this problem?
Thanks for your help.
Arash