I hope this is the right place to post this. I know Xillinux is by Xillybus so I thought this would be the best place.
I have a Zynq 7000 Development board and have been using Vivado 2014.4 to create a design using the Programmable Logic (PL). I have been using Xilinux as the embedded environment. My Vivado design is not using any Xillybus IP cores.
My question is: I have successfully generated a bitstream (.bit file) from my Vivado design and would like to continue using Xilinux as the Linux distribution. Since I implemented custom logic and added some peripherals, do I need to also generate a new BOOT.bin and device tree so that Xilinux will recognize the changes in the hardware? Or does the new bitstream handle all of that? The reason I am confused is because in the "Getting Started Xilinux for Zynq -7000 EPP" guide it says the following:
Additional HDL files with custom logic designs may be added to the project presented in paragraph 3.5, and then rebuilt the same way it was done the first place. To boot the system with the updated logic, copy the new xillydemo.bit into the (Micro)SD’s card’s boot partition, overwriting the existing one
That seems to imply that if I create custom logic that all I need to do is copy the new bitstream to the SD card. Will Xilinux know about the new peripherals I added in my design from the bitstream file alone or do I need to update the device tree and/or BOOT.bin file?
I am new to FPGA so I'm sorry if this is a dumb question. Any help would be very much appreciated.
Thanks,
Chris