Hi, Eli,
I tried revision B but the Address/data interface (16 address bits) of revision B does not work. You can write_mem and hexdump but no change can be seen after writing value to address.
// Memory array
reg [31:0] demoarray[0:31];
// Wires related to /dev/xillybus_mem_32
wire user_r_mem_32_rden;
wire user_r_mem_32_empty;
reg [31:0] user_r_mem_32_data;
wire user_r_mem_32_eof;
wire user_r_mem_32_open;
wire user_w_mem_32_wren;
wire user_w_mem_32_full;
wire [31:0] user_w_mem_32_data;
wire user_w_mem_32_open;
wire [15:0] user_mem_32_addr;
wire user_mem_32_addr_update;
// A simple inferred RAM
always @(posedge bus_clk)
begin
if (user_w_mem_32_wren)
demoarray[user_mem_32_addr] <= user_w_mem_32_data;
if (user_r_mem_32_rden)
user_r_mem_32_data <= demoarray[user_mem_32_addr];
end
assign user_r_mem_32_empty = 0;
assign user_r_mem_32_eof = 0;
assign user_w_mem_32_full = 0;
The original version is good. Do you have any clue is anything is wrong or there is a bug?
Best,
Chongxi