by support »
Hello,
Indeed, what you described is how the loopback works.
You can't use xillybus_pcie only, because it depends on xillybus_core. Accordingly, there will be no device files to access.
It looks like you want to write your own PCIe endpoint regardless of Xillybus. I don't think Xillybus is a good reference for that purpose, even though its simple use may make it look appealing. It's actually the other way around: Xillybus' design under the hood is quite complex in order to make the user experience simple. If you're making your own design, you probably want to make the design as simple as possible, at the expense of a less general-purpose user interface.
If that's indeed the case, I would warmly suggest trying to get help on Xilinx' forums, as you will get a wider response. This forum focuses on Xillybus and basic questions about PCIe.
Regards,
Eli