Hello,
I need an idea of implementation of PCIe endpoint on ML605 board.
My concept is,
I am taking video streaming from at 640*480p to my FPGA, from there i need send that data to PC (host) via PCIe interface.
I have created an endpoint using IP coregen (Xilinx RAM Memory Controller : 6011) and implemented it on a FPGA, When FPGA board is connected to PC it is detected successfully.
Please help me how to give data to that endpoint in FPGA and send it to PC.
I have already seen xapp1052 and implemented as shown..
Everything according to mannual completed successfully..
My actual doubt is..according to the image provided in the attachment..
Middle FPGA is main Controller FPGA..
The data from the all other 4 FPGA's will be tranferred to main Controller FPGA...and that data to be transmitted to PC(host) via PCIe..
The simple endpoint implementation from IP core in main Controller FPGA will not do as required....
So iam asking idea how to transfer data.......
Plz Help me..