by support »
I see.
Well, as I mentioned, PCIe is a bus. So when you write (as in *p = a) to an address within the range mapped to a PCIe card, a write request packet is generated by the root complex (i.e. the processor or memory controller chip). When you read from such an address (as in a = *p) a read request is sent, and a completion waited for. In reality, these operations are wrapped by calls such as iowrite32() (in Linux) to make the casts to volatile pointers and handling memory barriers and caches properly. But deep down, you'll have a plain memory write or read using a pointer.
So the packets aren't generated by software. To the programmer, the PCIe bus is just another chunk of memory. Or I/O space, if you insist on being old-fashioned.
I see.
Well, as I mentioned, PCIe is a bus. So when you write (as in *p = a) to an address within the range mapped to a PCIe card, a write request packet is generated by the root complex (i.e. the processor or memory controller chip). When you read from such an address (as in a = *p) a read request is sent, and a completion waited for. In reality, these operations are wrapped by calls such as iowrite32() (in Linux) to make the casts to volatile pointers and handling memory barriers and caches properly. But deep down, you'll have a plain memory write or read using a pointer.
So the packets aren't generated by software. To the programmer, the PCIe bus is just another chunk of memory. Or I/O space, if you insist on being old-fashioned.