by support »
Hello,
Short answer: You can always use a 3DW header, regardless of whether the data is aligned or not. The PCIe spec forbids the use of a 4DW header for addresses below the 4GB region, so Altera's PCIe block must support that (and indeed it does).
As for how to generate these packets, please refer to figure 8-16 in the document you referenced.
True, in the Appendix A of that document, where they show the TLP format for general information, they chose to put "Reserved" where there is possibly data. Either way, it's not relevant, because the Stratix PCIe block moves the first DW around to (partly) conform with the Avalon-ST view of data alignment. So when preparing the packets for the Avalon-ST interface, it doesn't matter what the actual TLP will look like.
Regards,
Eli
Hello,
Short answer: You can always use a 3DW header, regardless of whether the data is aligned or not. The PCIe spec forbids the use of a 4DW header for addresses below the 4GB region, so Altera's PCIe block must support that (and indeed it does).
As for how to generate these packets, please refer to figure 8-16 in the document you referenced.
True, in the Appendix A of that document, where they show the TLP format for general information, they chose to put "Reserved" where there is possibly data. Either way, it's not relevant, because the Stratix PCIe block moves the first DW around to (partly) conform with the Avalon-ST view of data alignment. So when preparing the packets for the Avalon-ST interface, it doesn't matter what the actual TLP will look like.
Regards,
Eli