by support »
Hello,
I take it that the IP core you're using implements the PCIe interface itself, rather than using the FPGA's own PCIe block(s). Because if your case is the latter, my advice would be to look for a serious problem in the core's configuration, or wiring, clocking, power supplies or something of that sort: If the PCIe link isn't up and running like easy-peasy, the problem isn't subtle. For example, the FPGA is expecting a reference clock on the wrong pin.
Actually, this is probably what I would look for even when using a core that implements the PCIe low-level stuff. Delving into the details is not likely to help.
Another thing: "But the simulation works" is a common misconception. The simulation proves very little. It's when it doesn't work, that you can be pretty sure that you have a problem. But when the simulation shows everything is fine, there are still a lot of pitfalls that the simulation won't show you.
OK, so to your question: The PCIe spec defines the LTSSM (Link Training and Status State Machine) in section 4.2.5. I suppose "Physical layer up" means that it's in the L0 state. But most PCIe cores expose the exact state of the LTSSM. If anywhere, this is where there's a hint on what went wrong.
Likewise, the state machine for the Data Link layer is defined in section 3.2, and I suppose "Link Layer established" would correspond to the DL_Up.
Regards,
Eli
Hello,
I take it that the IP core you're using implements the PCIe interface itself, rather than using the FPGA's own PCIe block(s). Because if your case is the latter, my advice would be to look for a serious problem in the core's configuration, or wiring, clocking, power supplies or something of that sort: If the PCIe link isn't up and running like easy-peasy, the problem isn't subtle. For example, the FPGA is expecting a reference clock on the wrong pin.
Actually, this is probably what I would look for even when using a core that implements the PCIe low-level stuff. Delving into the details is not likely to help.
Another thing: "But the simulation works" is a common misconception. The simulation proves very little. It's when it doesn't work, that you can be pretty sure that you have a problem. But when the simulation shows everything is fine, there are still a lot of pitfalls that the simulation won't show you.
OK, so to your question: The PCIe spec defines the LTSSM (Link Training and Status State Machine) in section 4.2.5. I suppose "Physical layer up" means that it's in the L0 state. But most PCIe cores expose the exact state of the LTSSM. If anywhere, this is where there's a hint on what went wrong.
Likewise, the state machine for the Data Link layer is defined in section 3.2, and I suppose "Link Layer established" would correspond to the DL_Up.
Regards,
Eli