by Guest »
Hi,
The scenario is x8 PCIE lane(no lane reversal),
1: lane 0,lane 2,lane 7 is not working then root complex train the link as x4 used
i.e., lane 1,3,4,5 act as lane0,1,2,3 .Is it correct?
2: lane 3 is not working then root complex train the link as x4 used
i.e.,lane 4,5,6,7 act as lane 0,1,2,3. Is it correct?
3: lane 3 is not working then root complex train the link as x2 used
i.e.,lane 0,1 act as lane 0,1, and all other lanes are inactive. Is it correct?
Regards,
SmRa
Hi,
The scenario is x8 PCIE lane(no lane reversal),
1: lane 0,lane 2,lane 7 is not working then root complex train the link as x4 used
i.e., lane 1,3,4,5 act as lane0,1,2,3 .Is it correct?
2: lane 3 is not working then root complex train the link as x4 used
i.e.,lane 4,5,6,7 act as lane 0,1,2,3. Is it correct?
3: lane 3 is not working then root complex train the link as x2 used
i.e.,lane 0,1 act as lane 0,1, and all other lanes are inactive. Is it correct?
Regards,
SmRa