by support »
Hello,
It looks a bit like you're trying to adopt C programming techniques in Verilog. The synthesizer probably ended up with something less than optimal. You need to feed it with a spoon, otherwise it messes up.
An array in Verilog is considered a hint to produce a memory. What you actually wanted was many registers. Maybe the synthesizer produced those registers, given that all element in the array are accessed by combinatoric logic simultaneously. So maybe this turned out OK, after all.
But if you produced some logic function, based upon 18 pieces of data, and made the "result" signal out of that, and all this using combinatoric dependencies only (no registers in the middle), no wonder you failed timing. You need to pipeline a bit. This issue is beyond the scope of this forum, and I suggest getting help possibly in Xilinx'. But to make a long story short: You need to get some intermediate registers in the middle.
As for your use of Xillybus, it would have been more logic-style to have the FPGA accept 18 elements through a regular (non-address) stream, and then emit the result to another stream in the other direction, once the result is ready. But that's a matter of style and needs.
Regards,
Eli
Hello,
It looks a bit like you're trying to adopt C programming techniques in Verilog. The synthesizer probably ended up with something less than optimal. You need to feed it with a spoon, otherwise it messes up.
An array in Verilog is considered a hint to produce a memory. What you actually wanted was many registers. Maybe the synthesizer produced those registers, given that all element in the array are accessed by combinatoric logic simultaneously. So maybe this turned out OK, after all.
But if you produced some logic function, based upon 18 pieces of data, and made the "result" signal out of that, and all this using combinatoric dependencies only (no registers in the middle), no wonder you failed timing. You need to pipeline a bit. This issue is beyond the scope of this forum, and I suggest getting help possibly in Xilinx'. But to make a long story short: You need to get some intermediate registers in the middle.
As for your use of Xillybus, it would have been more logic-style to have the FPGA accept 18 elements through a regular (non-address) stream, and then emit the result to another stream in the other direction, once the result is ready. But that's a matter of style and needs.
Regards,
Eli