by jeasinema »
I've got some problem with xillybus, and here are the descriptions:
1. During the kernel loading processing, it report a debug message :"xillybus_of 50000000.xillybus: No response from FPGA. Aborting."
2. Xilinux boots successfully, but I cannot find the xillybus devices in /dev/.
Some infos which may be useful:
1. I use Xilliux-1,3 with a zedboard-like Zynq-7020 board.
2. I use a vivado project generated by a Tcl script in xillinux-eval-zedboard-1.3c.zip(verilog version)
3. I've made some essential modifications in the project, then generated a bitstream and fsbl.elf
4. I rebuilt u-boot, then generate boot.bin with fsbl.elf built at 3
5. I built devicetree using this tutorial:http://www.wiki.xilinx.com/Build+Device+Tree+Blob, here is the part about xillybus:
- Code: Select all
amba_pl {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
ranges;
xillybus@50000000 {
compatible = "xillybus,xillybus-1.00.a";
interrupt-parent = <0x3>;
interrupts = <0x0 0x1e 0x4>;
reg = <0x50000000 0x1000>;
xlnx,dphase-timeout = <0x8>;
xlnx,max-burst-len = <0x100>;
xlnx,native-data-width = <0x40>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x40>;
xlnx,use-wstrb = <0x1>;
dma-coherent;
};
xillybus_lite@50002000 {
compatible = "xillybus,xillybus_lite_of-1.00.a";
interrupt-parent = <0x3>;
interrupts = <0x0 0x1d 0x1>;
reg = <0x50002000 0x1000>;
};
xillyvga@50001000 {
compatible = "xlnx,xillyvga-1.0";
reg = <0x50001000 0x1000>;
xlnx,dphase-timeout = <0x8>;
xlnx,max-burst-len = <0x10>;
xlnx,native-data-width = <0x20>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x20>;
xlnx,use-wstrb = <0x1>;
};
};
Thanks in advance!
I've got some problem with xillybus, and here are the descriptions:
1. During the kernel loading processing, it report a debug message :"xillybus_of 50000000.xillybus: No response from FPGA. Aborting."
2. Xilinux boots successfully, but I cannot find the xillybus devices in /dev/.
Some infos which may be useful:
1. I use Xilliux-1,3 with a zedboard-like Zynq-7020 board.
2. I use a vivado project generated by a Tcl script in xillinux-eval-zedboard-1.3c.zip(verilog version)
3. I've made some essential modifications in the project, then generated a bitstream and fsbl.elf
4. I rebuilt u-boot, then generate boot.bin with fsbl.elf built at 3
5. I built devicetree using this tutorial:http://www.wiki.xilinx.com/Build+Device+Tree+Blob, here is the part about xillybus:
[code]
amba_pl {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
ranges;
xillybus@50000000 {
compatible = "xillybus,xillybus-1.00.a";
interrupt-parent = <0x3>;
interrupts = <0x0 0x1e 0x4>;
reg = <0x50000000 0x1000>;
xlnx,dphase-timeout = <0x8>;
xlnx,max-burst-len = <0x100>;
xlnx,native-data-width = <0x40>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x40>;
xlnx,use-wstrb = <0x1>;
dma-coherent;
};
xillybus_lite@50002000 {
compatible = "xillybus,xillybus_lite_of-1.00.a";
interrupt-parent = <0x3>;
interrupts = <0x0 0x1d 0x1>;
reg = <0x50002000 0x1000>;
};
xillyvga@50001000 {
compatible = "xlnx,xillyvga-1.0";
reg = <0x50001000 0x1000>;
xlnx,dphase-timeout = <0x8>;
xlnx,max-burst-len = <0x10>;
xlnx,native-data-width = <0x20>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x20>;
xlnx,use-wstrb = <0x1>;
};
};
[/code]
Thanks in advance!