by Guest »
Hi, dear elites,
I am going to develop a ZYBO embedded HW prototype and would like to leverage the xillydemo for fast development. Thus, I decided to trace the xillydemo bundle design for ZYBO first and so I have some questions after tracing the xillydemo 1.3 project below.
Q1: In the xillydemo example project, it provides the following features (I don't list the xillybus_audio and xillybus_smb) :
/dev/xillybus_mem_8 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_read_32 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_read_8 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_write_32 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_write_8 (/dev/uio?, what's the uio no. ? )
Xillybus Lite (/dev/uio?, what's the uio no. ? )
Would you please explain how many Linux UIO devices it can support ? And what's the mapping b/w the HW and corresponding /dev/uioX ?
Q2: However, the project only instantiates one xillybus_lite_0 and one xillybus_ip_0 module separately. From this part, can we say it can support 2 Linux UIO devices ?
I am get stuck by Q1 & Q2 now.
Q3: How can user do the simulation in Xilinux sim. env ? Any reference ?
Q4: What's the speed of xillybus_clk ? Is it 125MHz as AXI lite ?
Q5: Is user_clk the same frequency to xillybus_clk in the demo project ?
With regard to my plan, I decide to leverage the xillydemo project with some customized modifications to meet our spec with as less effort as possible i.e. don't reinvent the wheel Xillybus contributes. I list my plan below and welcome any suggestions to make the plan right. Thanks
Spec:
1.Add the co-processor DSP IP in the demo project and leverage your xillybus ip (either xillybus_lite_0 or xillybus_ip_0) as interface. The register access is 32 bits for performance. The co-processor has 10 32-bit registers for configuration and maybe 1024x16 bits SRAM for buffer.
Q4: Do you suggest if I directly modify the related signals of xillybus_read_32 and xillybus_write_32 which uses xillybus_ip_0 to achieve the above spec which is the min. effort ? And the xillybus_clk is 125MHz ?
2.Need an AXI DMA to move data from DRAM or 256KB On-Chip Memory to the SRAM buffer of co-processor before enabling the co-processor to operate DSP function.
Q5: Do you suggest if I add an extra AXI DMA into the IP block in vivado_system.bd created by you which is the min. effort to meet the goal ?
3.The decoded output of the co-processor will update status register and CPU and access through the register read/write.
The implementation should be included as Q4 mentioned.
Appreciate and welcome for any inputs which can make it with as less effort as possible. Thanks
All the best,
Nan-Sheng
Hi, dear elites,
I am going to develop a ZYBO embedded HW prototype and would like to leverage the xillydemo for fast development. Thus, I decided to trace the xillydemo bundle design for ZYBO first and so I have some questions after tracing the xillydemo 1.3 project below.
Q1: In the xillydemo example project, it provides the following features (I don't list the xillybus_audio and xillybus_smb) :
/dev/xillybus_mem_8 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_read_32 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_read_8 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_write_32 (/dev/uio?, what's the uio no. ? )
/dev/xillybus_write_8 (/dev/uio?, what's the uio no. ? )
Xillybus Lite (/dev/uio?, what's the uio no. ? )
Would you please explain how many Linux UIO devices it can support ? And what's the mapping b/w the HW and corresponding /dev/uioX ?
Q2: However, the project only instantiates one xillybus_lite_0 and one xillybus_ip_0 module separately. From this part, can we say it can support 2 Linux UIO devices ?
I am get stuck by Q1 & Q2 now.
Q3: How can user do the simulation in Xilinux sim. env ? Any reference ?
Q4: What's the speed of xillybus_clk ? Is it 125MHz as AXI lite ?
Q5: Is user_clk the same frequency to xillybus_clk in the demo project ?
With regard to my plan, I decide to leverage the xillydemo project with some customized modifications to meet our spec with as less effort as possible i.e. don't reinvent the wheel Xillybus contributes. I list my plan below and welcome any suggestions to make the plan right. Thanks
Spec:
1.Add the co-processor DSP IP in the demo project and leverage your xillybus ip (either xillybus_lite_0 or xillybus_ip_0) as interface. The register access is 32 bits for performance. The co-processor has 10 32-bit registers for configuration and maybe 1024x16 bits SRAM for buffer.
Q4: Do you suggest if I directly modify the related signals of xillybus_read_32 and xillybus_write_32 which uses xillybus_ip_0 to achieve the above spec which is the min. effort ? And the xillybus_clk is 125MHz ?
2.Need an AXI DMA to move data from DRAM or 256KB On-Chip Memory to the SRAM buffer of co-processor before enabling the co-processor to operate DSP function.
Q5: Do you suggest if I add an extra AXI DMA into the IP block in vivado_system.bd created by you which is the min. effort to meet the goal ?
3.The decoded output of the co-processor will update status register and CPU and access through the register read/write.
The implementation should be included as Q4 mentioned.
Appreciate and welcome for any inputs which can make it with as less effort as possible. Thanks
All the best,
Nan-Sheng