by support »
Hello.
Answering your questions with matching numbers:
1) 'eof' is held zero, because the demo bundle shows an infinite loopback stream, and hence should never send an EOF to the host. The cited paragraph describes when eof may be asserted, not that it must be.
2) Once again, this paragraph says what's allowed. It's up to the application logic to make the choices what to do.
3) Note that all of the FIFO's ports that are related to writing to the FIFO are connected to Xillybus' user_w_write_32_* signals, and all FIFO read data ports to user_r_read_32_*. Consequently, Xillybus' IP core pushes arriving data from the write_32 stream to the FIFO, and fetches data to send to read_32 from the same FIFO. All in all, data is looped back from write_32 to read_32.
Regards,
Eli
Hello.
Answering your questions with matching numbers:
1) 'eof' is held zero, because the demo bundle shows an infinite loopback stream, and hence should never send an EOF to the host. The cited paragraph describes when eof [b]may[/b] be asserted, not that it must be.
2) Once again, this paragraph says what's allowed. It's up to the application logic to make the choices what to do.
3) Note that all of the FIFO's ports that are related to writing to the FIFO are connected to Xillybus' user_w_write_32_* signals, and all FIFO read data ports to user_r_read_32_*. Consequently, Xillybus' IP core pushes arriving data from the write_32 stream to the FIFO, and fetches data to send to read_32 from the same FIFO. All in all, data is looped back from write_32 to read_32.
Regards,
Eli