by Guest »
So I'm working on the design for a Xilinx FPGA + Xillybus system that might have 24 channels requiring 48 named pipes, one for each direction of the main data. I need command-and-control (C&C) as well. I could have an ADDITIONAL set of 48 named pipes, one for each direction of the C&C. But this brings my total number of name pipes, as well as total number of FIFOs on the FPGA, to a whopping 96. Alternatively, I could put all my C&C onto a single pair of named pipes, or I could take a partial position and put the C&C onto three pairs of named pipes (because those 24 channels are of three different types). These alternatives reduce my total number of named pipes and FPGA FIFOs by about a factor of two, but they increase complexity as multiple linux threads might be needing to independently exercise C&C and, with the C&C being over a shared channel, sharing and collision complications arise.
What are your thoughts about which way to go?
So I'm working on the design for a Xilinx FPGA + Xillybus system that might have 24 channels requiring 48 named pipes, one for each direction of the main data. I need command-and-control (C&C) as well. I could have an ADDITIONAL set of 48 named pipes, one for each direction of the C&C. But this brings my total number of name pipes, as well as total number of FIFOs on the FPGA, to a whopping 96. Alternatively, I could put all my C&C onto a single pair of named pipes, or I could take a partial position and put the C&C onto three pairs of named pipes (because those 24 channels are of three different types). These alternatives reduce my total number of named pipes and FPGA FIFOs by about a factor of two, but they increase complexity as multiple linux threads might be needing to independently exercise C&C and, with the C&C being over a shared channel, sharing and collision complications arise.
What are your thoughts about which way to go?