by support »
Hello,
This warning can be ignored safely. The issue is with the EDIF file which is included in the Xillybus block design component, however this doesn't cause any confusions if the replacement of the block design with a custom one (from the IP Core Factory) is done according to the instructions.
Regards,
Eli
Hello,
This warning can be ignored safely. The issue is with the EDIF file which is included in the Xillybus block design component, however this doesn't cause any confusions if the replacement of the block design with a custom one (from the IP Core Factory) is done according to the instructions.
Regards,
Eli