by support »
Hello,
Transceivers have their own clocking resources with rules on which PLL can be used with which transceiver and what routing resources can be used etc. Odds are that the transceivers you've allocated for the optic channel require clocking resources that conflict with the PCIe's transceivers, and things get messy. I'm surprised that you didn't get some really nasty warnings from the tools.
You might delve into the documentation on the matter, or alternatively try to narrow the PCIe lane width, as long as your bandwidth requirements are met. Note that each Gen1 lane gives you ~200 MB/s of payload bandwidth, a Gen2 lane ~400 MB/s and Gen3 gives ~800 MB/s. Also note that Xillybus' eval bundle's setting isn't Gen3, so you can reduce lane count and increase speed without changing performance.
It might be helpful to reduce the speed to Gen1 only. Not sure about this, but that requires only one data clock rate, which might ease on the clock resources. A shot in the dark if everything else fails.
Xillybus' IP core is indifferent to the PCIe parameters (on Cyclone 10GX) as long as the interface width remains the same, so just change the PCIe block's setting and re-implement.
Regards,
Eli
Hello,
Transceivers have their own clocking resources with rules on which PLL can be used with which transceiver and what routing resources can be used etc. Odds are that the transceivers you've allocated for the optic channel require clocking resources that conflict with the PCIe's transceivers, and things get messy. I'm surprised that you didn't get some really nasty warnings from the tools.
You might delve into the documentation on the matter, or alternatively try to narrow the PCIe lane width, as long as your bandwidth requirements are met. Note that each Gen1 lane gives you ~200 MB/s of payload bandwidth, a Gen2 lane ~400 MB/s and Gen3 gives ~800 MB/s. Also note that Xillybus' eval bundle's setting isn't Gen3, so you can reduce lane count and increase speed without changing performance.
It might be helpful to reduce the speed to Gen1 only. Not sure about this, but that requires only one data clock rate, which might ease on the clock resources. A shot in the dark if everything else fails.
Xillybus' IP core is indifferent to the PCIe parameters (on Cyclone 10GX) as long as the interface width remains the same, so just change the PCIe block's setting and re-implement.
Regards,
Eli