Hi
Sorry, let me ask a rudimentary question.
I want to use custom Revision XXL Xillybus IP cores in a block design of xillydemo-vivado.
My device is "Xilinx Virtex-7 FPGA VC709 Connectivity Kit" which is connected to host PC installed Ubuntu 18.04.1 LST.
I have already downloaded "Xillybus for PCIe" for VC709 (xillybus-eval-virtex7-gen3-2.0d) from the download page.
Then, by running xillydemo-vivado.tcl under "blockdesign" file on Vivado 2019.1.3, I generated a block design of xillydemo, and the bit stream generated from it runs normally on my device.
I confirmed that writing and reading using "/dev/xillybus_read_8" and "/dev/xillybus_write_8" files can be performed on the host PC.
Then, I wanted to apply a custom IP core of Revision XLL acquired from The Custom IP Core Factory to xillydemo.
I have added the following Device files to this core:
[Name/Direction/Data width/Expected BW/Autoset/Details]
xillybus_read_256 /Upstream (FPGA to host)/256 bits / 3200 MB/s /Yes/Data acquisition / playback (10 ms)
xillybus_write_256/Downstream(host to FPGA)/256 bits/ 3200 MB/s/Yes/Data acquisition / playback (10 ms)
I downloaded it and ran "insertcore.tcl" in "xillybus_block" folder on the design block of xillydemo.
An IP core on the block design is updated successfully, but a file containing the "pcie_v7_8x_xxl" module required in xillybus_block.v cannot be found and the bit stream cannot be generated.
Although the existence of the "pcie_v7_8x.v " file containing the" pcie_v7_8x "module can be confirmed, but it seems that the bit width of several wires ore register do not match and it cannot be used as it is.
Did something go wrong with my steps?
Please tell me how to make it work on xillydemo.