by whennig »
Hi Eli,
Thanks for the quick answer. I'm not intentionally trying to regenerate the core.
I skipped sections 3.3 and 3.4. All I did in ISE after opening the xise file was to click “Generate Programming File” or 'Synthesis"
ISE then gives me the message that it's trying to regenerate the core, but it fails as described below.
My guess is that the cores are outdated compared to the supported version in my ISE, and it wants to do something about that,.
So, if I actually go into "Manage cores" and look at the 2 fifo cores , they are described as
" this core was generated for [spartan 6] on 27-Mar-2013
type FIFO generator
version 6.2
identifier xilinx.com:ip:fifo:6.2 this core does not exist within the repository. a more recent version is available.
<actually bold>
"
below that I can select "upgrade to latest version and regenerate under current settings"
which upgrades them to version 9.3
The pcie core has a similar message, just different versions -- it's now upgraded to version 2.4
When I now try to compile, ISE does not give me the regeneration popups any more
However, a bunch of errors type 267 occur for xillybus.v lines 98-118,
"cannot find PORT trn_rd [and similar] on this module"
These lines are the ports to the pcie core.
When I find pcie.v from the generated core, I see these nets declared as wires within the pcie module, but the module's I/O ports are AXI signals and a lot of fc_ and cfg_ lines, no trn_ lines.
There is a comment in xillybus.v just above that about a perl snippet to turn I/O ports to wires "so only those that are really connect something become real ports". Do I have make those changes?
This is again using ISE 14.5
Thanks for your help,
Wolfgang
Hi Eli,
Thanks for the quick answer. I'm not intentionally trying to regenerate the core.
I skipped sections 3.3 and 3.4. All I did in ISE after opening the xise file was to click “Generate Programming File” or 'Synthesis"
ISE then gives me the message that it's trying to regenerate the core, but it fails as described below.
My guess is that the cores are outdated compared to the supported version in my ISE, and it wants to do something about that,.
So, if I actually go into "Manage cores" and look at the 2 fifo cores , they are described as
" this core was generated for [spartan 6] on 27-Mar-2013
type FIFO generator
version 6.2
identifier xilinx.com:ip:fifo:6.2 this core does not exist within the repository. a more recent version is available.
<actually bold>
"
below that I can select "upgrade to latest version and regenerate under current settings"
which upgrades them to version 9.3
The pcie core has a similar message, just different versions -- it's now upgraded to version 2.4
When I now try to compile, ISE does not give me the regeneration popups any more
However, a bunch of errors type 267 occur for xillybus.v lines 98-118,
"cannot find PORT trn_rd [and similar] on this module"
These lines are the ports to the pcie core.
When I find pcie.v from the generated core, I see these nets declared as wires within the pcie module, but the module's I/O ports are AXI signals and a lot of fc_ and cfg_ lines, no trn_ lines.
There is a comment in xillybus.v just above that about a perl snippet to turn I/O ports to wires "so only those that are really connect something become real ports". Do I have make those changes?
This is again using ISE 14.5
Thanks for your help,
Wolfgang