The Xillybus Forum

Hello,

This is Xilinx' mapper which has gone a bit too far with optimizing the design. This is essentially a bug in the tools, which tends to appear in particular when there are pins of an IP core that aren't used by the application logic. So the mapper gets eager to cut away unused logic, and at some point confuses itself.

Odds are that there is some Xillybus interface that you didn't use, possibly the one that you just generated. Note that it isn't enough to connect it to some wires in a module, but it has to be used to the extent that it has some effect on the outer world. Otherwise, the tools detect that noone will see if the logic is removed, and which case the logic [b]is[/b] optimized away.

Regards,
Eli

Hi Eli and all,

I want to create a device which reads the status from FPGA to host (my system will update the status of current operation to be read by host).

There are no synthesized error, however I got a [b]mapping error[/b], and attached below are the properties of my created device (from IP Core Factory) followed by the error (there are 64 errors which are almost similar). Could anyone point me what should I done? Thanks a lot.

Device name: [b]xillybus_status_32[/b]
Direction: [b]upstream (FPGA to host)[/b]
Data width: [b]32-bit[/b]
Expected bandwidth: [b]102.400 kB/s[/b]
Autoset: [b]Yes[/b]
Details: [b]Command and Status[/b]

[code]LUT6 symbol
"xillybus_ins/xillybus_core_ins/wr_arbiter_ins/Mmux_wr_arb_state[2]_sendbuf_data[31]_wide_mux_45_OUT91" (output
signal=xillybus_ins/xillybus_core_ins/wr_arbiter_ins/wr_arb_state[2]_sendbuf_
data[31]_wide_mux_45_OUT[17]) has an equation that uses input pin I5, which
no longer has a connected signal. Please ensure that all the pins used in the
equation for this LUT have signals that are not trimmed (see Section 5 of the
Map Report File for details on which signals were trimmed).[/code]