by Guest »
Hello Xillybus team,
Thank you for sharing useful contents inside your website.
I have a x4 pcie xilinx board, and I tried to use your IP core and driver to maintain a streaming pcie communication between windows and FPGA board, however when I brows the address of xillybus-windriver-1.2.0.0 folder, unfortunately it couldn't be recognized by the windows. while I checked this with Jungo windriver, the coniguration space containing one BAR was recognized by the software, alongside this, the link up flag went high correctly.
What I have changed from your project are just related to the lane number (x8 to x4). when creating VHDL based project, I found thatthere is a module (xillybus_core.v) which is empty. In addition, I tried to create a block design based project, it couldn't be built due to this file (NGC).
Is it something related to this?
I would appreciate if you help me to fix this issue.
Regards
Mim
Hello Xillybus team,
Thank you for sharing useful contents inside your website.
I have a x4 pcie xilinx board, and I tried to use your IP core and driver to maintain a streaming pcie communication between windows and FPGA board, however when I brows the address of xillybus-windriver-1.2.0.0 folder, unfortunately it couldn't be recognized by the windows. while I checked this with Jungo windriver, the coniguration space containing one BAR was recognized by the software, alongside this, the link up flag went high correctly.
What I have changed from your project are just related to the lane number (x8 to x4). when creating VHDL based project, I found thatthere is a module (xillybus_core.v) which is empty. In addition, I tried to create a block design based project, it couldn't be built due to this file (NGC).
Is it something related to this?
I would appreciate if you help me to fix this issue.
Regards
Mim