The Xillybus Forum

hello Eli,
So for building Boot.bin for Xillinux 2.0, can i use the u-boot binary of Xillinux-1.3 or if i have to generate u-boot-xillinux-2.0.elf, kindly guide me the process.

Regards,
Mojo

Hello,

Setting up the Device Tree is off this forum's topic. You may want to refer to this page: http://xillybus.com/tutorials/device-tree-zynq-1

Anyhow, the "aliases" part is just a list of aliases, short expressions for longer ones. The "spi0" alias isn't used otherwise in the file, so it doesn't matter if it's removed or not.

On the other hand, the entry it refers to, ps7_qspi_0, is the SPI interface for the QSPI flash, so you probably don't want to touch that entry.

I suggest getting more help in Xilinx' forums on this issue.

Regards,
Eli

[quote="eli"][quote="zer0c00l"]Do I have to build U-boot as well or can I just use the u-boot binary used in Xillinux-1.3[/quote]
Using the original U-boot binary is fine. Actually, recommended.[/quote]


I extracted the dts from a board running Xillinux. At the end of the file there is this section

[b]aliases {
spi0 = "/amba@0/ps7-qspi@e000d000";
serial0 = "/amba@0/serial@e0001000";
ethernet0 = "/amba@0/ps7-ethernet@e000b000";
};[/b]

Now should I remove the line [b]spi0 = "/amba@0/ps7-qspi@e000d000";[/b] after adding my own spi0 device.

[quote="zer0c00l"]Do I have to build U-boot as well or can I just use the u-boot binary used in Xillinux-1.3[/quote]
Using the original U-boot binary is fine. Actually, recommended.

[quote="eli"][quote="zer0c00l"]So if now I move to ISE to rebuilt FSBL. I will have to do edit the design again to enable the SPI in XPS right?[/quote]
Correct.[/quote]

Do I have to build U-boot as well or can I just use the u-boot binary used in Xillinux-1.3

[quote="zer0c00l"]So if now I move to ISE to rebuilt FSBL. I will have to do edit the design again to enable the SPI in XPS right?[/quote]
Correct.

So if now I move to ISE to rebuilt FSBL. I will have to do edit the design again to enable the SPI in XPS right?

Hello,

Changes made in the processor's configuration (enabling SPI in your case) require a rebuild of the FSBL and hence also the boot.bin. The way that the processor is informed on how it should treat its I/O wires is through software configuration setting registers, which is done by the FSBL.

As the original FSBL was built in the ISE suite, the recommended flow for obtaining a new one is to make the changes in XPS (part of the ISE suite) and build the FSBL file using the SDK attached to XPS. The processor's configuration in the files for Vivado is not accurate enough for rebuilding FSBL.

As for creating the boot.bin file, the u-boot binary used in Xillinux-1.3 can be downloaded from this link:

http://xillybus.com/downloads/u-boot-xillinux-1.3.elf.zip

If you want to rebuild U-boot yourself, please refer to /usr/src/xillinux/uboot-patches/README.TXT in Xillinux distribution's file system for how to obtain the sources used to compile U-boot for Xillinux. It's recommended to use Xilinx' cross compiler for this.

Regards,
Eli

I have managed to edit the original block design of Xillybus and enabled SPI0 on the PS. I have generated the modified bitstream, and now I have to rebuilt FSBL, and BOOT.bin. I have also gone through other forum post where [b]eli[/b] suggests that this should be done in XPS (ISE). Now I only have a license for Vivado, and I am running windows 10. I tried downloading ISE, but it was very buggy on Win 10, crashed very often. Is there any way to built FSBL using Vivado?