The Xillybus Forum

Hello,

Indeed, if you just connect some of the PS_GPIO[] pins to the FIFO's dout output, they are double driven, as you didn't disconnect them from their previous driver.

As I said before, I suggest making sure you understand how xillydemo.v works before attempting to make changes. The modification you made doesn't imply you've got to the bottom of it as of yet.

Logic design is a skill of its own, which requires quite some effort to acquire. However this forum deals with Xillybus-specific issues. There are plenty of other sources and forums for getting help with Verilog and logic design.

Regards,
Eli

Hi,

Thanks for your reply.

I tried to attach fifo's data output to JA1, one of Pmods. I have checked the constraint file called xillydemo.xdc. It says ports of JA1 are constrained to PS_GPIO[31:24]. In order to break the demo's loopback. I modified the code as:
[code]fifo_8x2048 fifo_8
(
.clk(bus_clk),
.srst(!user_w_write_8_open && !user_r_read_8_open),
.din(user_w_write_8_data),
.wr_en(user_w_write_8_wren),
.rd_en(user_r_read_8_rden),
.dout(PS_GPIO[31:24]),
.full(user_w_write_8_full),
.empty(user_r_read_8_empty)
);[/code]
But when I tried to rebuild the project, it failed in synthesis process because of those pins having multiple drivers. Could you please help me to point out where I did wrong?

Hello,

The loopback takes place in xillydemo.v or xillydemo.vhd (depending on which language you chose). Make sure you understand that module, and from there it should be clear how to take it from there.

Regards,
Eli

Hi all，

I am new to FPGA. I want wo use Xillinux as a interface to control Pmods on the PL side from PS side. However, I have looked through all the documentation and still confused about how I can break the loopback in the demo bundle and connect that FIFOs to those Pmod I/Os.

Regards,
Zihao