The Xillybus Forum

Hello,

Xillybus supplies a stream connection between the FPGA and host. If the application logic needs to access memory directly, other means should be used. It could be an AXI interface to on-board DDR memory, or on Zynq devices, to the ARM processor's memory space, via a separate AXI port.

The question is if the logic really needs to access the memory, or if the host program can feed it with data through dedicated streams. It depends of course on the algorithm implemented. However if the algorithm has no preknown data access pattern, implementing an efficient caching mechanism is likely to be the main issue.

I suggest taking a look on this page for some discussion on this topic:

http://xillybus.com/doc/future-xillyhpc

Note however that the project mentioned, XillyHPC, is currently not scheduled for implementation.

Regards,
Eli

Hi, dear support,

It seems that Xilinux demo bundle is a good kit to leverage to develop some rapid prototyping applications. However, if our application is related to machine learning or AIs, it implies that the hardware accelerator under development requires to fetch the data sets from memory for further processing. Thus, I'd like to inquire if there is any suggestion about this. Is it possible to enable the hardware accelerator with xillybus interface and also can access DRAM or on-chip memory via the AXI bus of Xillybus demo bundle kit? Or is it adequate to use the Xillybus demo bundle to develop hardware accelerator which needs to access DRAM or on-chip RAM? If it can support, we can introduce to students for final projects in our course this semester. If yes, which documents do you refer for reference?

Thanks