The Xillybus Forum

Hello,

The fifo_pre_* and fifo_post_* signals from the deepfifo module should go to the signals with the respective names of the pre and post FIFO. Your application logic connects to the other side of these FIFOs.

As for the instantiation parameters, it depends on configuration of the MIG module.

Regards,
Eli

Hi xillybus,
I am a newbie. Your link http://xillybus.com/tutorials/deep-virtual-fifo-download-source is good for me.
I use a MIG for "MT4KTF25664HZ-1G9" DDR3.

1. Can you give me an example for deepfifo's instantiation parameters?
2. Now, i use:
- fifo_full from Pre FIFO
- fifo_empty from Post FIFO
use for DeepFIFO. Is it wrong?

Please correct me.
Thanks a lot.