by support »
Hello,
If the board doesn't supply the 50 MHz and 125 MHz clocks, they can be generated from another free-running clock by virtue of a PLL. This is discussed in the IP Compiler for PCI Express User Guide, page 166:
https://www.intel.com/content/dam/www/p ... xpress.pdfTo make a long story short, the 125 MHz frequency is mentioned explicitly in the user guide, and it must be free-running and independent of the PCIe reference clock. However it can be derived from another free-running clock, and same goes for the 50 MHz clock.
There's a caveat, though: The PLL lock. The said user guide discusses this and explains how to deal with this issue.
Regards,
Eli
Hello,
If the board doesn't supply the 50 MHz and 125 MHz clocks, they can be generated from another free-running clock by virtue of a PLL. This is discussed in the IP Compiler for PCI Express User Guide, page 166:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf
To make a long story short, the 125 MHz frequency is mentioned explicitly in the user guide, and it must be free-running and independent of the PCIe reference clock. However it can be derived from another free-running clock, and same goes for the 50 MHz clock.
There's a caveat, though: The PLL lock. The said user guide discusses this and explains how to deal with this issue.
Regards,
Eli