Hi,
I am new to PCIe. I have read through a lot of the spec and have just bought the Mindshare book (PCI Express Technology), which is very good.
But I have one nagging question, and it is probably just something I'm not understanding.
The book talks about the 6 BARs in the EP and how you set the lower bits to specify the type and size of memory the system software needs to assign to it. It then talks about the upper bits then being written to by the system software with the base address for the EP. Any downstream TLPs within the range allocated to it will be processed by the EP.
I also see that the BARs in a switch have base and limit reg to help forward TLPs to an EP below.
But what about if I want to do an upstream mem write, and write to the system memory attached to the RP? What is the base and limit address for writing upstream? Where is this set and how do I find out what it is, so that I can set the correct address when I create a mem write TLP at the EP to go to the RP and system memory? I am basically trying to stream data to a PC from a PCIe card I have.
I must be missing something obvious...
Thanks