Hi Eli,
I'm in the process of designing a Artix 7 based board with x1 PCIe. I went through the schematics of a few artix 7 boards, where they have tied the PCIE_PRSNT#1 and PCIE_PRSNT#2 signals together, and in some cases where there is a 4 lane, there is a jumper to select between 1x and 4x which is tied to the PCIE_PRSNT#1 on the top.
While I have previously used ML505, in that board, the same signal is connected via a NMOS to a FPGA pin.
Why is there this difference ? Has it got to do with the electromechanical specs of PCIe (I'm not able to get these documents !)
Which one should I follow ? I plan on using xillybus, and from previous experience, xillybus requires only PCIE_PERST, the clocks and the data pins.
Also, What are the consequences of not using the WAKE# ? Does it just block my ability to use hot-plugging/swapping ? I also see that most boards of xilinx with pcie effectively leave the wake signal open.
I would be grateful for any clarification !
Thanks !
Mugundhan