Hi,
I have an ML605 Virtex 6 board and have used the Xillybus interface with it quite a bit. I want to try a 16X to 1X PCIe riser, which looks like it just takes any type PCIe up to 16X and downsizes it to one lane. Are there any modifications I need to make to the demo bundle to make something like this work? I was thinking I might have to remove some of the lanes in the .ucf file, but I seem to recall PCIe can auto detect how many lanes are active. Can Xillybus do the same?
Thanks,
Michael