I have used the Xillybus with a 32-to-16 FIFO to stream data from the PC to my design. By placing an ILA at the output of the FIFO and capturing the data and empty signal, I am finding that the FIFO is empty about half the time. I am only running my design at 10MHz which seem like it should almost never go empty given the speed of the PCIe? Any suggestions?
Gabriel