How to build PCIe IP core on custom board
Posted:
Hi,
I am new to FPGA and am trying to build PCIe on a custom board with only 1 lane available. The board is based on Virtex 6 and will be used for data acquisition. I have tried to use the xillybus demo on ML605 board and the demo runs perfect. However, when I tried to use the IP core factory to build a custom IP core, there is no place to define the number of lanes.
So is there any documentation showing how and where to change or modify the number of the lanes to be used? Where is the file to define the custom board pin out and other configuration (like bus_clk?)
Thanks for any help!
Jason
I am new to FPGA and am trying to build PCIe on a custom board with only 1 lane available. The board is based on Virtex 6 and will be used for data acquisition. I have tried to use the xillybus demo on ML605 board and the demo runs perfect. However, when I tried to use the IP core factory to build a custom IP core, there is no place to define the number of lanes.
So is there any documentation showing how and where to change or modify the number of the lanes to be used? Where is the file to define the custom board pin out and other configuration (like bus_clk?)
Thanks for any help!
Jason