Dear Xillybus forum
I am building a network interface card using INTEL PCIE Hard IP. INTEL delivers a testbench for simulation, that only sends 4 Octets (octet = 8bit) from the Rootpoint (host) over the serial (gen2 x 4) interface to an application in the EndPoint (the FPGA). Thanks to your very clear desciption of how PCIE works and the TLP's, I managed to change the testbench and application such, that it sends WritePackets of any length <= Max Payload, sends ReadRequests, and sends back from the application Completion Packets.
However, So far, the host initiated the traffic: it writes data , then it sends a ReadRequest, then the application answers with a Completion TLP.
Now, the FPGA wants to initiate traffic: it received a chunk of data, and wants to send it to the host. I see an inefficient way to do this: the host keeps sending ReadRequests, until Data has arrived, and the EndPoint sends a Completion TLP with the data, answering the most recent ReadRequest. The unanswered ReadRequests just dissappear.
The better way, I think, is that the EndPoint initiates the transmission to the host. But i cannot find how this is done. Please advice.
Thanks, Pieter