Hello,
I really appreciate your site on explaining (sort of dumbing down) the PCIe. As you mentioned the Spec. is a bit overwhelming.
I am currently troubleshooting test hardware we have developed to act as a PCIe device to connect to another device (root) for testing purposes. The PCIe test device is a Northwest Logic core we have purchased on a Xilinx FPGA. In simulation my FPGA developer shows that the core is working correctly, and we know the root also works correctly with the real hardware that we are trying to emulate with our test hardware.
When I look at the various signals on the FPGA, I do see that the PHY Layer Up and Link Layer Up signals never get asserted. There appears to be an issue perhaps at the physical layer and possibly at the link layer.
What I am trying to find, is the protocol or definition of how PCIe determines 1: a Physical Layer has been established, 2: a Link Layer has been established
Any links or information you could provide on that would be greatly appreciated.
Thank you
Establishing successful PICe link
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Re: Establishing successful PICe link
by support »
Hello,
I take it that the IP core you're using implements the PCIe interface itself, rather than using the FPGA's own PCIe block(s). Because if your case is the latter, my advice would be to look for a serious problem in the core's configuration, or wiring, clocking, power supplies or something of that sort: If the PCIe link isn't up and running like easy-peasy, the problem isn't subtle. For example, the FPGA is expecting a reference clock on the wrong pin.
Actually, this is probably what I would look for even when using a core that implements the PCIe low-level stuff. Delving into the details is not likely to help.
Another thing: "But the simulation works" is a common misconception. The simulation proves very little. It's when it doesn't work, that you can be pretty sure that you have a problem. But when the simulation shows everything is fine, there are still a lot of pitfalls that the simulation won't show you.
OK, so to your question: The PCIe spec defines the LTSSM (Link Training and Status State Machine) in section 4.2.5. I suppose "Physical layer up" means that it's in the L0 state. But most PCIe cores expose the exact state of the LTSSM. If anywhere, this is where there's a hint on what went wrong.
Likewise, the state machine for the Data Link layer is defined in section 3.2, and I suppose "Link Layer established" would correspond to the DL_Up.
Regards,
Eli
I take it that the IP core you're using implements the PCIe interface itself, rather than using the FPGA's own PCIe block(s). Because if your case is the latter, my advice would be to look for a serious problem in the core's configuration, or wiring, clocking, power supplies or something of that sort: If the PCIe link isn't up and running like easy-peasy, the problem isn't subtle. For example, the FPGA is expecting a reference clock on the wrong pin.
Actually, this is probably what I would look for even when using a core that implements the PCIe low-level stuff. Delving into the details is not likely to help.
Another thing: "But the simulation works" is a common misconception. The simulation proves very little. It's when it doesn't work, that you can be pretty sure that you have a problem. But when the simulation shows everything is fine, there are still a lot of pitfalls that the simulation won't show you.
OK, so to your question: The PCIe spec defines the LTSSM (Link Training and Status State Machine) in section 4.2.5. I suppose "Physical layer up" means that it's in the L0 state. But most PCIe cores expose the exact state of the LTSSM. If anywhere, this is where there's a hint on what went wrong.
Likewise, the state machine for the Data Link layer is defined in section 3.2, and I suppose "Link Layer established" would correspond to the DL_Up.
Regards,
Eli
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