Hello,
I customized a core in IP factory, downloaded it and generated the PCIe End-point core's verilog files again in 13.1 as I'm using virtex-5. Then, I import the generated verilog files along with the top module, xillybus_ins and xillybus_core_ins to my design in ISE 14.7, where I use the design in my top module which is a schematic. The synthesis goes correctly, but when I'm implementing the design, I get an ngbuild error, saying that ISE is unable to find the xillybus_ins/xillybus_core_ins, while I'm able to see it in the heirarchy. But when I imported the xillybus_core_ins.ngc file with the xillybus_core_ins.v also in heirarchy, the design gets implemented successfully without any error. But when I compiled previous designs using the core with the demo bundle, i used only the xillybus_core_ins.v (I didn't instantiate the .ngc file), but still my design compiled.
1.) Why is this?
2.) Is this expected behaviour ?
P.S.: Also I get a warning saying that the .ngc file is for the sx50T device, can this be ignored ? or can this be changed in anyway ?
Thanks !
Mugundhan