I previously had success with the demo bundle by running the verilog .tcl and clicking generate_bitstream in vivado.
Now I have started over, this time planning to experiment with attaching my own app logic. I cleared out the project, ran the .tcl again, but this time when I try to elaborate, synthesize, or implement I receive the fatal error:
- Code: Select all
[Synth 8-439] module 'pcie_k7_vivado_pipe_clock' not found ["C:/Users/sam/Desktop/xillybus-eval-virtex7-1.2d/vivado-essentials/pcie_k7_8x_pipe_clock.v":51]
Anyone know how I should address this issue or why I am now seeing this error? If I remember correctly I repeated the exact same steps from the guide which were once successful. But it's possible I'm forgetting a step.
Thank you.