Hi,
I am using an independent clock FIFO with the write clock being 250MHz and read clock as 125MHz. The write clock is the bus_clk which is the same as given in demo project. I am using a PLL to generate the read clock of 125MHz. In order to consider the two clocks as asynchronous, I am not sure how to set the constraints in Vivado. Which clock should be used as source for 250MHz clock? Is it the bus_clk or the user_clk1 from which bus_clk actually comes from? Can anyone provide me some suggestions.
Thanks