Hi All,
We implemented an FIFO to access the SPI on the FPGA, the communication works okay except some behavior that I am getting. Below are the pseudo commands on how I communicate to the SPI.
1. open the device (xillybus_spi)
2. write spi commands
3. read the data
#For some reason, the pipe has some left over data, so I added the command below to empty the pipe.
4. read data until I get the EOF before proceeding to step 5.
5. close the device.
The behavior that I was having is that doing the #4 and for unknown reason (the pipe is empty), the read function never return and never received the EOF signal.
My questions:
1. Is there a way that every time my program open or close the device, the driver (xillibus) will throw away the left over data?
2. Does the FPGA able to detect if the device has been opened or closed then send a signal to the xillybus driver to throw away the left over data?.
3. If the pipe is empty, is there any kind of configuration setting that we can add in FPGA that if the pipe is empty, send EOF?.
Regards,
John